1. Field
This invention relates to the art of electronic design automation (EDA), and more specifically to an automated design process and chip description system.
2. Related Art
In the art of semiconductor chip design, tools such as electronic design automation (EDA) are used to provide a means for automating the design of Integrated Circuits (IC) and Systems on a Chip (SoC) so that the design can be tested prior to the expensive process of implementing the design in silicon. Tools are also provide a means of automating the task(s) of preparing the design for manufacture on silicon.
Hardware Description Languages (HDL) are used to model a chip and its functions. Existing HDL technology places the main functional description of Integrated Circuits (IC) and Systems on a Chip (SoC) in Register Transfer Language (RTL) source files.
The RTL source files do not include information about various non-functional aspects of the design. Such non-functional aspects include voltages, clock rates, etc. Specifically, such source files do not have a provision to express control of the design using voltage states. Hence, it is not possible to simulate, synthesize, perform physical design or formally verify a design with multiple voltage states at the RTL and gate-level abstractions without manual intervention to compensate for the loss of voltage-related information. Non-functional aspects of the design are typically described in constraint (input/output) files and scripts; text documents and email messages; oral communications between design team members and other members of the project team; tags; spreadsheets; and programs, formats and databases that are not necessarily directly connected to the databases that are used for implementation and verification.
What is needed is a system and method that compensates for the loss in design information that occurs when the design is represented in traditional functional descriptions.